EDN

Design Compiler FPGA

The Best FPGA Synthesis for ASIC Prototyping–Design Once!Design Compiler FPGA is the only solution available today that is targeted specifically for designers who prototype ASICs using high-end FPGAs.
Business Wire

Starbridge and Impulse Collaborate on C-to-FPGA Acceleration

KIRKLAND, Wash. & SALT LAKE CITY--(BUSINESS WIRE)--Starbridge Systems and Impulse Accelerated Technologies today announced a joint initiative to provided graphical and C-language tools for ...
Houston Chronicle

(BW) VMETRO FPGA Design Kit Accelerates DSP Development for Xilinx(R) Virtex(TM)-5 FPGAs

With the V5+C kit, software application developers who may be less familiar with low-level VHDL design methods can easily move ANSI C algorithms to an FPGA-accelerated platform. Experienced hardware ...
EDN

Reducing FPGA Compile Time Using Parallel Compilation Methodology

Compile time for large designs has been a major bottleneck since FPGAs were first created. Reducing compile time offers a large benefit to users as their designs can be turned around quickly by ...
WatersTechnology

Impulse Announces C-to-HDL FPGA Compiler

Impulse Accelerated Technologies has announced the latest version of its C-to-HDL compiler, providing field-programmable gate array (FPGA) coding support for Arista Switch users. FPGAs, which are ...
Design-Reuse

Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and Xilinx FPGAs

Integration Enables High-level Synthesis of Mixed Control/Datapath Designs and Incremental Synthesis for FPGAs SAN JOSE, Calif., and TOKYO, 20 Jan 2009-- Cadence Design Systems, Inc. (NASDAQ: CDNS), ...
Electronic Design

Updated C-to-FPGA Compiler Accelerates Image Processing

Version 3.7 of CoDeveloper C-to-FPGA compiler includes performance improvements, wider Linux support, and more parallel hardware optimization features including higher-throughput streaming I/O. Other ...
Institutional Investor

Impulse Launches Improved FPGA Compiler

Impulse Accelerated Technologies has unveiled a new version of its CoDeveloper C-to-FPGA Optimizing Compiler. The enhanced CoDeveloper 3.7 offers timing optimizations that speed up generated pipelines ...
Design-Reuse

PROGRAMMABLE LOGIC: Compiler turns FPGAs into supercomputers

Santa Cruz, Calif. — Scientists, engineers and software developers who know nothing about chip design can now compile high-performance computing applications into FPGAs, according to startup ...
Hackaday

FPGA Retrocomputer: Return To Moncky

Part of the reason that retrocomputers are still so popular despite their obsolescence is that it’s possible to understand the entire inner workings of a computer like this, from the transistors all ...
Electronic Design

3D FPGA Takes On 100G Networking

Tabula's original ABAX introduced its 3D SpaceTime architecture to the FPGA world (see FPGAs Enter The Third Dimension). The ABAX 2 series is implemented using Intel's 22nm Tri-Gate technology (see ...